RTL Design Engineer

Client: RTL Design Engineer - 4-6 Yrs

Location: Hyderabad

No. Of Positions: 1

Experience: 4-6 years

The Job Summary:

We are seeking a Design Engineer 2 with 4-6 years of experience in RTL design, subsystem integration, and silicon quality signoff. The ideal candidate will develop high-quality RTL, drive IP/subsystem integration, and ensure design readiness through rigorous quality checks including Lint, CDC, RDC, synthesis, and handoff validation. Candidates should be passionate about design quality, automation, and delivering production-ready RTL with minimal debug cycles

Key Responsibilities

RTL Design Integration

• Develop synthesizable RTL using Verilog/SystemVerilog for complex digital IPs and subsystems.
• Translate architecture specifications into scalable microarchitectures and robust RTL implementations.
• Integrate multiple IPs into subsystem and SoC environments while ensuring functional correctness.
• Implement and debug AMBA-based interfaces including AXI4, AXI4-Lite, AHB, and APB.
• Drive clocking, reset, address mapping, and configuration integration activities.

RTL Quality Ownership

• Own RTL quality from development through design handoff.
• Ensure compliance with RTL coding guidelines, design methodologies, and signoff requirements.
• Perform detailed RTL reviews and identify functional, structural, and methodology issues.
• Drive resolution of quality violations before verification handoff.
• Champion "clean RTL" practices and first-pass silicon success.

Static Quality Checks Signoff

• Drive closure of:
  • Lint violations
  • CDC (Clock Domain Crossing) violations
  • RDC (Reset Domain Crossing) violations
  • X-propagation issues
  • Structural RTL checks
  • Synthesis warnings/errors
  • Design rule violations
• Analyze CDC/RDC reports and work with architecture and verification teams to resolve root causes.
• Ensure proper synchronizer implementation and clock/reset domain handling.
• Perform quality assessments before RTL freeze and milestone signoffs.

Handoff Readiness Validation

• Own RTL handoff checklist completion before verification and implementation.
• Ensure:
  • Clean Lint signoff
  • Clean CDC/RDC signoff
  • Synthesis-ready RTL
  • Protocol compliance validation
  • Register specification alignment
  • Clock/reset architecture compliance
• Review integration dependencies and eliminate late-stage quality escapes.

Design Automation Methodology

• Develop scripts and automation to improve RTL quality and productivity.
• Create dashboards, reports, and automated quality metrics tracking.
• Automate repetitive quality checks and regression analysis.
• Contribute to enhancement of team-wide RTL development and signoff methodologies.

Improve design review processes and quality gates.