Rtl Design Engineer

Hiring Design Engineer for Product based company (RTL Design & Quality Ownership)
We're looking for a highly motivated Design Engineer with 4-6 years of experience in RTL design, subsystem integration, and silicon-quality signoff.

Key Skills:
Verilog/SystemVerilog RTL Design
IP/Subsystem/SoC Integration
AMBA Protocols (AXI4, AXI4-Lite, AHB, APB)
Lint, CDC, RDC Closure
Synthesis & RTL Signoff
Clock/Reset Architecture
RTL Quality Reviews & Handoff Readiness
Python/TCL/Perl Automation (preferred)

Responsibilities:
Develop high-quality synthesizable RTL
Drive IP and subsystem integration
Own RTL quality from development to handoff
Drive closure of Lint, CDC, RDC, X-propagation, and synthesis issues
Ensure clean signoff and production-ready RTL
Improve RTL development methodologies through automation