RTL Design Engineer - SoC
Cyient · Hyderabad · onsite · Posted 50d ago
Undisclosed4–9 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
- Experience: 6-9 years.
- Good knowledge on the digital concepts and ASIC flow
- Experience in RTL coding
- Must have hands on experience with SoC design and integration.
- The candidate worked on ARM SoCs
- Peripherals including high speed ones like PCIe, USB
- Developing UPF with multiple power domains, including conducting UPF checks and power aware simulations
- Experience in Verilog/System-Verilog is a must.
- Basic knowledge on verification , functions and tasks
- Understanding of Memory controller designs
- Must have experience in Synthesis / Understanding of timing concepts
Roles and Responsibilities
Under direct supervision, performs engineering work and applied research, development, and design of new Integrated Chips. Work includes Architectural Design, Logic Design, Circuit Design, Physical Design, Verification, Fabrication, Packaging of Chips.
Sourced from naukri
Skills
SOCi2cUSBverificationLecsoc designphysical designsynthesiscSimulationCircuit designingVerilogSystem VerilogLogic designSystemFPGAASICPCIEVHDLRTL CodingRTL DesigncircuitReact Testing LibraryIC DesignC plus plusdigitalUPFArchitectural DesignTimingASIC SynthesisSoCsIntegration
About Cyient

Cyient
IT Services & Consulting
11.9k+
employees
1991
35 years old
Hyderabad/Secunderabad, Telangana
India
About
Cyient delivers engineering solutions addressing digital and sustainable futures, serving a diverse client base while promoting cultural and environmental responsibility.
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