RTL Design Engineer : Bangalore

Key Responsibilities & Requirements:

• Strong experience in Logic Design and RTL Coding.
• Hands-on experience in SoC Design and Integration for complex SoCs.
• Proficiency in Verilog/SystemVerilog.
• Strong understanding of Multi-Clock Designs and Asynchronous Interfaces.
• Experience with ASIC development tools and methodologies, including Lint and CDC.
• Knowledge of Synthesis and Timing Concepts is an added advantage.
• Experience in ECO Fixes and Formal Verification.
• Good understanding of AMBA protocols, including AXI, AHB, and APB.
• Strong knowledge of SoC Clocking and Reset Architecture.
• Ability to debug complex RTL and integration issues and collaborate effectively with cross-functional teams.

Interested can share resume on [email removed]