RTL Design and Verification Engineer

Job Summary

RTL design and constrained-random verification for digital and mixed-signal parts.

Job Type: Full time

Experience: 3 8 years

Location: Bengaluru, India

The Work

What the role involves

• RTL implementation against a specification, with clock and reset architecture designed rather than inherited.
• UVM testbench development, coverage closure and formal property verification where it fits.
• DFT awareness, because test structures change timing and area.

Skills

• SystemVerilog
• UVM
• RTL
• Coverage
• Formal
• DFT

Common Questions

Where is this role based

Bengaluru, India. Full time.

What experience is expected

3 8 years. The range is a guide rather than a filter make the case if you are outside it.

Disclaimer: This job posting and location has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.