Ramaiah Academy Foundation
Ramaiah Academy Foundation · Bengaluru · onsite · Posted 38d ago
About a minute. You'll make an account on the way through.
About this role
Role & responsibilities
Experience and Qualification:
Qualification: B.E./B.Tech Experience: 5 + Years (Industry Experience is an added advantage)
Roles & Responsibilities:
• Strategic Leadership & Curriculum Architecture: Define the technical roadmap for the VLSI division. Design, audit, and continuously upgrade high-quality, industry-aligned curricula, assignments, and advanced project frameworks covering Digital Design through to STA.
• Program Delivery & Master Instruction: Deliver high-impact, advanced classroom and online training sessions on complex topics including SystemVerilog OOP, UVM testbench architectures, constrained random verification, and advanced Static Timing Analysis (STA).
• Team & Lab Management: Supervise and mentor a team of Application Engineers and trainers. Oversee the setup, deployment, and maintenance of industry-grade EDA tool flows within the Academys laboratories.
• Project Mentorship & Evaluation: Architecture and guide real-time, tape-out quality capstone projects (e.g., RISC-V processors, high-speed interconnects, or hardware accelerators). Establish rigorous evaluation standards and interview preparation strategies.
• Industry Collaboration: Foster deep relationships with semiconductor companies, design houses, and EDA vendors to align training paradigms with contemporary industry constraints and placement demands. Skill
Requirements:
• Core Technical Expertise: Authoritative knowledge of Verilog, SystemVerilog, advanced RTL design principles (FSM design, clock domain crossing, low-power design), and advanced computer architecture.
• Verification Mastery: Deep-dive expertise in the Universal Verification Methodology (UVM), SystemVerilog Assertions (SVA), Functional Coverage modelling, and building complex, reusable constrained-random verification environments.
• Implementation & Sign-off: Thorough understanding of RTL Synthesis, Synopsys Design Constraints (SDC) generation, and Static Timing Analysis (STA) closure methodologies.
• EDA Tool Suite Proficiency: Expert-level command over industry-standard EDA tools from Cadence or Synopsys (e.g., VCS, Verdi, Design Compiler, PrimeTime, Spyglass, Formality, Xcelium, or Genus).
• Soft Skills & Pedagogy: Exceptional communication, lecturing, and leadership skills with a passion for knowledge transfer, talent development, and technical writing.
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