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    Job · 21090238

    BENGALURU · FULLTIME

    PRINCIPAL PHYSICAL VERIFICATION ENGINEER

    Nxp

    Nxp

    Bengaluru · onsite · Posted 7d ago

    Sourced fromFoundit
    Not disclosedFresherfulltimeBengaluru

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    Section · 01

    About this role

    We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.

    Key Responsibilities

    • Perform physical verification (PV) for block-level and full-chip designs, including:
      • Design Rule Check (DRC)
      • Layout Versus Schematic (LVS)
      • Electrical Rule Check (ERC)
      • Antenna, density, and reliability checks
    • Drive signoff closure by identifying and resolving PV violations efficiently.
    • Work with physical design and layout teams to debug and fix violations.
    • Develop and maintain runsets, decks, and automation flows using industry-standard tools.
    • Analyze foundry decks and PDK updates, ensuring compliance with process requirements.
    • Lead tapeout readiness reviews and ensure high-quality database delivery.
    • Perform hierarchical verification and regression management.
    • Participate in improving verification methodologies, runtime, and capacity optimization.
    • Interface with foundry and EDA vendors to resolve tool or deck-related issues.
    • Mentor junior engineers and review their work as needed.

    Preferred / Added Advantage Skills

    • Exposure to Physical Design (PD) concepts, including:
      • Floorplanning (macro placement, block shaping, congestion awareness)
      • Power Delivery Network (PDN) design (power grid, IR drop considerations)
    • Understanding of:
      • Placement, CTS, routing flows
      • PD-PV interaction and impact of layout decisions on DRC/LVS closure
    • Knowledge of:
      • EM/IR, latch-up, ESD reliability checks
      • Multi-patterning / EUV constraints
    • Experience with full-chip integration and SoC-level challenges
    • Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
    • Exposure to flow automation and methodology development

    Soft Skills

    • Strong analytical and problem-solving ability
    • Effective communication across cross-functional teams
    • Ownership mindset with focus on quality and timelines
    • Ability to work independently and guide team members

    #LI-29f4

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    Section · 02

    Skills

    Hierarchical verificationAntenna density and reliability checksEM IR latch-up ESD reliability checksFlow automation and methodology developmentFoundry decks and PDK updatesMulti-patterning EUV constraintsPlacement CTS routing flowsRunsets decks and automation flowsSoC-level challengesVerification methodologies runtime and capacity optimizationRegression managementfull-chip integration

    Section · Company

    About NXP Semiconductors

    Nxp

    Nxp

    Semiconductors

    1.8k+

    employees

    1969

    57 years old

    Eindhoven

    NL

    About

    NXP is a global semiconductor company creating solutions that enable secure connections for a smarter world.

    Industries

    AppsAutomotiveEnergy EfficiencyInformation TechnologyManufacturingMobile

    Employee ratings

    380 reviews

    3.6/ 5

    Culture

    3.6

    Career growth

    2.9

    Work-life

    3.7

    Employees rate it well for

    Work Life Balance54Work Culture44Salary32Senior Management27Learning25

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