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    Job · 20637108

    BENGALURU · FULLTIME

    PRINCIPAL PHYSICAL VERIFICATION ENGINEER

    Kinara

    Kinara

    Bengaluru · onsite · Posted 12d ago

    Sourced fromNaukri
    Undisclosed4–8 yrsfulltimeBengaluru

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    Section · 01

    About this role

    We are seeking a talented Physical Verification Design Engineer to join our VLSI design team. This role involves ownership of full-chip and block-level physical verification (PV) signoff, ensuring designs meet foundry and reliability requirements. The candidate will collaborate closely with physical design, PDK, CAD, and tapeout teams to deliver high-quality silicon.
    Key Responsibilities
    • Perform physical verification (PV) for block-level and full-chip designs, including:
      • Design Rule Check (DRC)
      • Layout Versus Schematic (LVS)
      • Electrical Rule Check (ERC)
      • Antenna, density, and reliability checks
    • Drive signoff closure by identifying and resolving PV violations efficiently.
    • Work with physical design and layout teams to debug and fix violations.
    • Develop and maintain runsets, decks, and automation flows using industry-standard tools.
    • Analyze foundry decks and PDK updates, ensuring compliance with process requirements.
    • Lead tapeout readiness reviews and ensure high-quality database delivery.
    • Perform hierarchical verification and regression management.
    • Participate in improving verification methodologies, runtime, and capacity optimization.
    • Interface with foundry and EDA vendors to resolve tool or deck-related issues.
    • Mentor junior engineers and review their work as needed.
    Preferred / Added Advantage Skills
    • Exposure to Physical Design (PD) concepts, including:
      • Floorplanning (macro placement, block shaping, congestion awareness)
      • Power Delivery Network (PDN) design (power grid, IR drop considerations)
    • Understanding of:
      • Placement, CTS, routing flows
      • PD-PV interaction and impact of layout decisions on DRC/LVS closure
    • Knowledge of:
      • EM/IR, latch-up, ESD reliability checks
      • Multi-patterning / EUV constraints
    • Experience with full-chip integration and SoC-level challenges
    • Ability to correlate PV issues with PD root causes (e.g., spacing, density, routing hotspots)
    • Exposure to flow automation and methodology development
    Soft Skills
    • Strong analytical and problem-solving ability
    • Effective communication across cross-functional teams
    • Ownership mindset with focus on quality and timelines
    • Ability to work independently and guide team members

    More information about NXP in India...
    #LI-29f4

    Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

    Sourced from naukri

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    Section · 02

    Skills

    design rule checkAutomationSOCVLSIphysical designlvsregressionPVdesign engineerVLSI DesignCADEvent DrivenFoundryDebugPhysical Verificationcompliance

    Section · Company

    About Kinara

    Kinara

    Kinara

    Biotechnology

    None

    CU

    ₹25L PA avg

    Avg at Kinara

    About

    Kinara delivers unrivaled edge AI solutions to accelerate and optimize real-time decision-making by powering smart edge devices and gateways that demand responsive AI computing at high energy efficiency. The company focuses on innovative technologies that enhance performance and energy efficiency in AI applications. By providing comprehensive support and training, Kinara ensures customers can effectively utilize their products and solutions.

    Industries

    AI InfrastructureArtificial Intelligence (AI)Computer VisionSemiconductorSoftware

    Employee ratings

    6 reviews

    3.8/ 5

    Culture

    3.7

    Career growth

    3.2

    Work-life

    3.8

    Employees rate it well for

    Company Culture45Work-Life Balance43

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