Principal Engineer SoC Design Verification

Job Summary

Principal SoC Verification

The Principal SoC Verification Lead provides technical leadership for verification of complex Smart Analog Sensor SoCs. The role is responsible for verification strategy, methodology, planning, execution, and signoff across subsystem and full-chip environments. This individual will drive verification quality across processor, accelerator, memory, connectivity, and sensor subsystems while ensuring comprehensive coverage and first-silicon success.

At MIPS by GF Custom Silicon Business, verification is a critical component of product success. We are committed to building robust, scalable and reusable verification environments that ensure first-pass silicon success.

Key Responsibilities

• Development of chip-level and subsystem-level verification strategies
• Definition of test plans, coverage plans and verification methodologies including UVM
• Leadership of verification engineers across internal and external resources
• Lead verification of interfaces, bus interconnects, DMA engines, memory architectures, security and safety functions, data processing pipelines, peripherals and application use cases
• Coordinate subsystem and SoC-level verification activities
• Development of scalable verification infrastructure and automation
• Collaboration with architects and designers throughout the development cycle
• Cross-functional coordination with physical design, emulation and other related engineering teams
• Ownership of verification closure and signoff readiness

Verification Strategy

• Define verification architecture for complex SoCs.
• Develop verification plans aligned with architecture and product requirements.
• Establish signoff criteria and coverage closure methodology.

Environment Development

• Lead development of UVM-based verification environments.
• Define reusable verification components and infrastructure.
• Drive scalable verification frameworks across multiple SoC programs.

SoC Verification Leadership

• Lead verification of CPU subsystems
• Interconnects
• DMA engines
• Memory architectures
• Security and safety functions
• Sensor data processing pipelines

Coverage Metrics

• Drive closure of:
• Functional coverage
• Code coverage
• Assertions
• Safety requirements coverage
• Define verification KPIs and dashboards

Technical Leadership

• Mentor senior verification engineers
• Lead reviews and verification signoff decisions
• Drive adoption of advanced verification methodologies

Required Qualifications

• Minimum BS and 15+ years of relevant industry experience
• Extensive experience in UVM-based verification
• Experience verifying complex SoCs
• Experience building reusable verification environments
• Experience defining and tracking coverage metrics

Preferred Qualifications

• Experience with emulation and prototyping
• Experience with safety and security verification
• Experience with performance verification
• Experience leading globally distributed teams

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.