Principal Engineer, DFT

As a Principal Engineer-DFT with Marvell, you ll be a member of the Connectivity business group. Connectivity solutions from Marvell help customers address the growing demands of AI, cloud computing, edge computing, 5G networks, and next-generation data centers. Engineers within the Connectivity Business Unit work on cutting-edge silicon design, firmware, software, system validation, and platform development, collaborating across global teams to deliver products that connect billions of devices and accelerate digital transformation.

Joining the Connectivity Business Unit offers the opportunity to work on complex technical challenges, influence next-generation connectivity technologies, and contribute to products deployed at global scale.

• Define and drive DFT architecture and implementation strategies for complex SoC/ASIC designs.
• Develop and implement scan, compression, MBIST, and other DFT features to achieve test coverage and manufacturing quality goals.
• Execute and support scan insertion, DFT verification, and ATPG flows.
• Collaborate closely with RTL, verification, physical design, timing, and product engineering teams throughout the design lifecycle.
• Create and maintain DFT-related timing constraints and signoff requirements.
• Perform DFT timing analysis and debug timing-related issues.
• Drive DFT methodology improvements and contribute to flow automation.
• Provide technical leadership and mentorship to junior engineers.

Required Qualifications

• Bachelors or Masters degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related field.
• 14+ years of experience in Design for Test (DFT) for ASIC/SoC development.
• Strong expertise in DFT methodologies, including scan architecture, scan compression, ATPG, Memory BIST, Boundary Scan and testability concepts.
• Hands-on experience with Siemens EDA Tessent tools.
• Strong experience with synthesis and scan insertion tools.
• Solid understanding and hands on experience of Static Timing Analysis (STA) and timing closure concepts.
• Experience creating and managing SDC (Synopsys Design Constraints) files for DFT implementation and timing signoff.
• Strong debugging, problem-solving, and analytical skills.
• Excellent communication and collaboration skills.

This role is eligible to participate in Marvells bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the companys long-term success. #LI-RV1