Principal Engineer, Design Verification Engineering

About Analog Devices

Analog Devices, Inc. (NASDAQ: ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI, and software technologies into solutions that combat climate change, reliably connect humans and the world, and help drive advancements in automation and robotics, mobility, healthcare, energy and data centers. With revenue of more than $11 billion in FY25, ADI ensures today's innovators stay Ahead of What's Possible. Learn more at and on and .

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• Lead end-to-end SoC verification for complex digital SoCs, driving execution from planning to signoff.
• Verify complex microprocessor-based designs, AI/ML accelerators, and high-speed peripherals using advanced verification methodologies.
• Define and drive team execution by planning tasks, tracking progress, and providing technical leadership, mentoring, and guidance.
• Collaborate closely with architecture and design teams to define requirements and align on verification deliverables and dependencies.
• Drive pre-silicon readiness by aligning with emulation, FPGA, and software teams to cover post-silicon validation scenarios early.
• Develop and execute end-to-end system-level use cases for comprehensive functional validation.
• Architect and implement scalable UVM-based testbenches, DV flows, and methodologies.
• Define and review test plans ensure closure of functional and code coverage across block, subsystem, and SoC levels.
• Work cross-functionally with emulation, FPGA, firmware, and system teams to ensure full-system correctness.
• Apply formal verification techniques for IP and subsystem-level validation.
• Lead NoC/interconnect verification and ensure robust data flow across the SoC.
• Perform performance verification and system-level analysis across real-world use cases.
• Drive innovation in verification strategies to meet aggressive schedules and quality goals.
• Define overall verification strategy based on product requirements and design specifications, leveraging modern techniques such as formal, emulation, portable stimulus, and virtual platforms.

• B.Tech/M.Tech with 12+ years of experience in digital pre-silicon verification, including leadership across IP, subsystem, or SoC-level DV.
• Strong understanding of SoC/Subsystem architectures with hands-on expertise in Verilog/SystemVerilog and UVM-based testbench development, debugging, and methodology implementation.
• Proven track record in verification closure using functional and code coverage metrics across block, subsystem, and SoC levels.
• Expertise in NoC, bus, and interconnect verification, along with coverage analysis and optimization.
• Experience in architecting scalable testbench environments and defining robust DV flows and methodologies.
• Strong background in power-aware verification (UPF), including power analysis and optimization.
• Hands-on experience with formal verification, including flow definition, connectivity, and functional property checking.
• Solid protocol knowledge and verification experience across high-speed and low-speed interfaces such as I2C, SPI, Ethernet, UART, AXI/AHB, DMA, and SVI3.
• Experience in security and safety verification, ensuring compliance with secure design and functional safety requirements.
• Familiarity with gate-level simulations with timing annotation (GLS).
• Strong expertise in test planning, constrained-random verification, assertions, and transaction-level modeling.
• Good understanding of processor-based systems (ARM, RISC-V, Tensilica), AI/ML accelerators, and proficiency in C/C++, SystemC, and scripting (Python/TCL/Shell).
• Exposure to mixed-signal/analog verification (ADC/DAC/PLL/PHY) is a plus.
• Excellent communication and leadership skills with the ability to collaborate across global teams and drive verification innovation.
• Strong problem-solving mindset with the ability to quickly learn and adopt new technologies