Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Education: BE/ B Tech/ ME/ M Tech / MS : Expr 6 – 15 (T3/T4) B.Tech/BE/ME/Mtech with hands-on experience physical design , timing closure and physical verification. Exp with ASIC design flow, hierarchical physical design strategies, methodologies and understand deep sub-micron technology issues. Solid knowledge on physical design flow, Timing closure and physical verification. Knowledge of formal verification, EM-IR . Good track records of working on complex IP’s & SoC’s below 7 nm  Power user of Cadence implementation tools, such as Genus, Innovus, Quantus,Tempus, PVS, Voltus. Automation and programming-minded, coding experience in Makefile/Tcl/Tk/Perl/Python. Any AI expr is add on. Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills. We’re doing work that matters. Help us solve what others can’t.