Principal Design Engineer
CDS Infra Projects · Pune · onsite · Posted 57d ago
About a minute. You'll make an account on the way through.
About this role
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BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
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7+ years of Design Verification experience with SV/UVM
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Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
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Design Verification experience verifying complex designs and leading projects from concept to verification closure.
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Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
We re doing work that matters. Help us solve what others can t.Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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About CDS Infra Projects
CDS Infra Projects
Engineering & Construction
Gurgaon / Gurugram, Haryana
India
₹8.3L PA avg
Avg at CDS Infra Projects
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