Principal ASIC Design Engineer

Principal ASIC Design Engineer in Bangalore, KA, India Description

Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra AI-Native embedded compute, Veros wireless connectivity, and multimodal sensing solutions. We re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play.

Synaptics is seeking a highly experienced Principal ASIC Design Engineer to provide technical leadership across SoC architecture, design, integration, verification, implementation, and silicon bring-up. This is a senior technical leadership role requiring deep expertise in digital ASIC/SoC design, low-power architecture, and system-level integration, along with a proven ability to solve complex technical problems and influence engineering decisions across multiple disciplines. You will drive critical SoC initiatives from architecture through production, working closely with Design, Verification, Physical Design, DFT, Systems, Firmware, and Software teams, serving as a technical authority for complex design and integration challenges, drive scalable design methodologies and best practices, mentor engineers, and help shape the technical direction of current and next-generation products. This position reports to the Sr. Director, ASIC Design.

Responsibilities & Competencies

Job Duties

• Provide technical leadership for the architecture, micro-architecture, and design, integration of complex ASIC/SoC products from concept through tape-out, silicon bring-up, and production
• Define and review SoC architecture, micro-architecture, clock/reset architecture, system interfaces, and integration requirements in collaboration with system architects and cross-functional engineering teams
• Drive key architectural and implementation decisions by balancing power, performance, area, cost, schedule, and design complexity (PPA
• Drive power analysis and optimization across architecture, RTL, and physical implementation in collaboration with designers, system architects, and implementation teams
• Provide technical leadership for RTL design and SoC integration, including coding quality, Lint, CDC/RDC, SDC, and design-quality closure
• Drive SoC integration and release quality with IP teams, ensuring IP and subsystem deliverables meet established design-quality criteria and program milestones
• Guide verification planning and methodologies, collaborating closely with the verification team to ensure functional correctness and coverage closure
• Partner with physical design teams on floorplanning, synthesis, STA, timing closure, congestion, power integrity, and PPA optimization, ensuring effective front-end/back-end convergence
• Serve as the technical point of escalation for complex pre-silicon and post-silicon issues, leading systematic root-cause analysis across hardware, firmware, software, and system boundaries
• Influence technical decisions across geographically distributed Design, Verification, Physical Design, DFT, Systems, Firmware, Software, Product, and Program Management teams
• Establish and promote engineering best practices for RTL coding, architecture and design reviews, documentation, integration, release criteria, and design quality

• Expert knowledge of ASIC/SoC design methodologies, low-power designs using UPF, including power domains, isolation, retention, power sequencing, and power-state management
• High proficiency in RTL coding (Verilog/SystemVerilog, VHDL) and simulation environments
• Strong knowledge of clock/reset architecture, lint, CDC/RDC, synthesis, STA, DFT, power analysis, and physical design considerations
• Strong knowledge of Perl/Python, Tcl scripting to improve design and verification efficiency
• Deep knowledge of industry-standard EDA methodologies and tools from Synopsys, Cadence, and/or Siemens EDA, including synthesis, STA, low-power, and design-quality flows
• Familiarity with physical design flows, constraints, and close interaction between front-end and back-end teams to root-cause complex issues at block, subsystem, and SoC levels
• Analytical and data-driven decision-making, with the ability to balance tradeoffs in complex systems.
• Ability to communicate complex, interactive design concepts clearly
• Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance
• Well organized with strong attention to detail; proactively ensures work is accurate
• Positive attitude and work ethic; unafraid to ask questions and explore new ideas
• Resourceful and able to solve highly complex problems through adaptation of existing technology and development of new technology with a deep understanding of product architecture
• Excellent written and verbal communication skills, with the ability to communicate effectively with engineers, senior leadership, customers, IP vendors, and external partners
• Ability to work within a diverse team and mentor developing team members

Qualifications (Requirements)