Physical Verification Engineer

We are looking for a skilled Physical Verification Engineer with hands-on experience in Siemens EDA (Mentor Graphics) Calibre IC Validator to support advanced semiconductor design verification activities. The candidate will be responsible for executing physical verification flows, ensuring foundry compliance, and working closely with layout, circuit design, and methodology teams to achieve tape-out quality designs.

Key Responsibilities

• Perform physical verification of custom and digital IC layouts using IC Validator.
• Execute and debug DRC (Design Rule Check), LVS (Layout Versus Schematic), ERC (Electrical Rule Check), and Antenna checks.
• Analyze and resolve physical verification violations in collaboration with layout and design engineers.
• Ensure compliance with foundry technology rules for advanced process nodes (28nm, 16nm, 7nm, 5nm, etc.).
• Develop and optimize physical verification runsets and automation scripts.
• Support full-chip and block-level verification signoff activities.
• Perform parasitic extraction validation and signoff checks.
• Work with PDK teams to understand and resolve technology-related verification issues.
• Drive tape-out readiness reviews and verification closure.
• Generate physical verification reports and provide design recommendations.

Required Skills

Strong experience with IC Validator (Synopsys) physical verification tool.

• Expertise in: 
• DRC
• LVS
• ERC
• Antenna Checks
• Density Checks
• Metal Fill Verification
• Understanding of semiconductor fabrication processes and design rules.
• Knowledge of CMOS technology and advanced semiconductor nodes.
• Experience with custom and/or digital layout verification.
• Familiarity with physical design and tape-out flows.
• Strong debugging and root-cause analysis skills.

Technical Skills

Tools: 

• Synopsys IC Validator
• Calibre (good to have)
• Virtuoso
• ICC2 / Fusion Compiler (good to have)
• StarRC (good to have)

Scripting: 

• Tcl
• Perl
• Python
• Shell Scripting