Physical Verification Engineer (Lead/Staff/Sr Staff) - Custom Silicon Group

Company

Qualcomm India Private Limited

Job Area

Engineering Group, Engineering Group > Hardware Engineering

General Summary

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
  
  

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Experience: 5 to 15 Years

Key Responsibilities

• Drive Physical Verification sign-off activities including DRC, LVS, Antenna, ERC, PERC, ESD, and related verification checks for advanced technology nodes.
• Collaborate closely with Physical Design, Custom Layout, and Foundry teams to ensure clean sign-off and physical convergence.
• Debug and resolve physical verification violations while driving closure to tape-out.
• Support methodology development, automation, and flow enhancements for sign-off quality and productivity.
• Participate in floorplanning, power planning, and PDN reviews to ensure robust physical implementation.
  
  

Required Skills

• Strong experience with Physical Verification sign-off flows and tools.
• Good understanding of PDK concepts, SVRF rule decks, Calibre, and ICV.
• Hands-on experience with Innovus, ICC2, Fusion Compiler, or equivalent implementation tools.
• Solid understanding of Physical Design implementation flow, layouts, and backend design methodologies.
• Experience working on advanced technology nodes such as 2nm, 3nm, 5nm, 7nm, or 10nm.
• Familiarity with Tech LEF, Design Rules, and Foundry PDKs.
• Strong debugging and problem-solving skills in sign-off environments.
  
  

Preferred Qualifications

• Experience in Floorplanning, Power Planning, and PDN design.
• Team leadership or people management experience.
• Automation skills using TCL, Perl, or scripting languages.
• Exposure to custom IC design flows and mixed-signal/SOC environments.
  
  

Nice to Have

• Experience driving physical convergence across multiple blocks or full-chip designs.
• Exposure to ESD reliability analysis and advanced PERC methodologies.
• Experience mentoring junior engineers and leading technical initiatives.
  
  

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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If you would like more information about this role, please contact Qualcomm Careers.