Physical Design Lead (RTL-GDSII)
Mirafra Technologies · Remote · remote · Posted 24d ago
Undisclosed4–9 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
- Own complete RTL-to-GDSII flow: floorplan, place, CTS, route, signoff
- Drive PPA optimization, timing, SI, IR/EM closure
- Lead and mentor a team of PD engineers; manage schedules and deliverables
- Interface with RTL, DFT, STA, Verification, Foundry, and Signoff teams
- Handle ECOs, tapeout readiness, and design reviews
- Improve PD methodologies, flows, and automation
- Strong hands-on PD expertise with Innovus / ICC2 / FusionCompiler / Tempus / PrimeTime /Etc.
- Experience in 28nm to 3nm nodes
- Solid scripting skills (TCL, Python/Perl/Shell)
- Proven ownership of block or full-chip tapeouts
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Sourced from naukri
Skills
AutomationScriptingSTAphysical designDesign LeadMentorPerlDFTReact Testing LibraryPython
About Mirafra Technologies
Mirafra Technologies
Semiconductors
832
employees
2004
22 years old
Bangalore/Bengaluru, Karnataka
India
About
Mirafra Technologies specializes in software development and silicon design services, addressing complex technological needs in various industries.
Industries
SemiconductorsHardware & NetworkingSoftware Product
Employee ratings
304 reviews
3.7/ 5
Culture
3.7
Career growth
3.3
Work-life
3.8
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