Physical Design Engineer

Navii is an AI recruiter, running this search on behalf of Proxelera.

HERE'S HOW IT WORKS

Rather than your resume sitting in a queue, you have a conversation with Navii about your experience and what you want next. What you say reaches Proxelera's hiring team in your own words. It is a required step, and there is nothing to schedule.

NEXT STEP

A conversation with Navii about this role:

https://app.heynavii.ai/careers/physical-design-engineer-4055cb57

ABOUT PROXELERA

Proxelera does end-to-end chip design from India, specification through silicon. Most chip companies use their India centres for validation or one slice of the process. Proxelera was built on the opposite idea: the whole system, owned ground up, in country. Over 190 engineers across the Bengaluru and Mysuru design centres, working on AI, DSP, AMS and wireless networking silicon.

THE ROLE

You will own the physical design process, guiding netlists through floorplan, placement, clock tree synthesis and route to sign-off, on AI, DSP, AMS and wireless networking silicon. This is end-to-end chip design, where you implement and also innovate.

Also a fit if you call yourself: Physical Design Engineer, Chip Design Engineer, VLSI Engineer.

THE WORK

• Lead the physical implementation of blocks or chips, holding timing closure across corners and modes.

• Manage constraints and SDC, run EMIR and IR-drop analysis, and take physical verification through sign-off.

• Work on schematic capture, layout, matching and parasitics on the analog side, contributing to both PD and implementation.

• Work closely with cross-functional teams, driving alignment and making sure designs meet customer specifications.

• Use TCL, Python or Perl to streamline the flow and keep productivity up.

WHAT YOU'LL NEED

• You have owned the physical implementation of a block or chip through to sign-off, managing timing closure in practice.

• You have written or corrected constraints and SDC rather than only consuming them.

• You have run the production flow through floorplan, placement, CTS and route, meeting all sign-off checks.

• You script well enough to hold the flow together, in TCL, Python or Perl.

EVEN BETTER IF

• You have handled DFT insertion, scan and ATPG during implementation.

• You are familiar with low-power implementation, including UPF and multiple power domains.

• You have worked at advanced nodes and understand the specific challenges they bring.

WHO THRIVES HERE

• You enjoy complex design challenges and want ownership of your work.

• You like a collaborative culture with open communication and feedback, and you adapt to what different teams need.

• You are proactive, and you improve processes as you hit new problems.

THE TEAM

You will join over 190 engineers across Bengaluru and Mysuru, working with stakeholders across the organisation. You will report to Raghavendra Mohan V, who leads delivery and operations.

COMPENSATION AND LOGISTICS

Full-time, on-site five days a week, Bangalore or Hyderabad. The hiring team will share compensation details directly. Benefits include health insurance, paid time off and professional development support.