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    Job · 16855830

    Cyient logo

    Physical Design Engineer

    Cyient · Bengaluru · onsite · Posted 41d ago

    Undisclosed3–8 yrsfulltimeSourced fromNaukri

    About a minute. You'll make an account on the way through.

    About this role

    Job Summary:**

    CYIENT SEMICONDUCTORS PRIVATE LIMITED is seeking a highly motivated and skilled Physical Design Engineer to contribute to the full lifecycle of ASIC/SoC physical implementation, from netlist to GDSII. This role involves tackling complex design challenges in advanced technology nodes and ensuring high-performance, low-power, and area-optimized designs.

    Job Responsibilities:**

    * Perform all aspects of physical design, including floor planning, power planning, place and route, clock tree synthesis (CTS), timing closure (STA), signal integrity analysis, and physical verification (DRC/LVS).
    * Collaborate with front-end design, DFT, and package teams to ensure successful integration and meet design specifications.
    * Analyze and resolve complex timing, power, and area issues through iterative physical design methodologies.
    * Develop and implement automation scripts to improve efficiency and productivity of physical design flows.
    * Participate in technology node evaluation and contribute to the definition of design methodologies and best practices.
    * Generate and review physical design documentation, including floor plans, timing reports, and physical verification results.
    * Mentor junior engineers and contribute to knowledge sharing within the team.

    Job Qualifications:**

    * Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
    * 3-8 years of hands-on experience in full-chip or block-level physical design for complex ASICs/SoCs.
    * Proficiency with industry-standard EDA tools for physical design (e.g., Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre).
    * Strong understanding of static timing analysis (STA) principles and tools (e.g., Synopsys PrimeTime, Cadence Tempus).
    * Solid knowledge of deep sub-micron technology issues, including signal integrity, power integrity, and DFM/DFX.
    * Experience with scripting languages such as Tcl, Perl, Python, or Shell scripting.
    * Familiarity with advanced technology nodes (e.g., 16nm, 10nm, 7nm, 5nm).
    * Excellent problem-solving, analytical, and communication skills.
    * Ability to work effectively in a team-oriented environment.

    Sourced from naukri

    Skills

    TechnologyBashStatic Timing AnalysisPrimetimeSTACadenceeda toolsphysical designlvsfloor planningtiming closuretclInnovussynthesisSUBDRCPerlIssueASICChipsMentor GraphicsEvent DrivensynopsysFusionPythonDrc / LvsCommunication Skillsanalyticalanalysis

    About Cyient

    Cyient logo

    Cyient

    IT Services & Consulting

    11.9k+

    employees

    1991

    35 years old

    Hyderabad/Secunderabad, Telangana

    India

    About

    Cyient delivers engineering solutions addressing digital and sustainable futures, serving a diverse client base while promoting cultural and environmental responsibility.

    Industries

    IT Services & ConsultingManufacturingEngineering & Construction

    Employee ratings

    5,322 reviews

    3.6/ 5

    Culture

    3.5

    Career growth

    2.9

    Work-life

    3.7

    Employees rate it well for

    Salary856Job Security557Work Life Balance497Work Environment494Senior Management467

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