Physical Design Engineer

Physical Design Engineer – 3+ Years

Job Summary

We are looking for a skilled Physical Design Engineer with 3+ years of experience in RTL-to-GDSII implementation. The candidate should have strong hands-on experience in physical design flows, timing closure, physical verification, and PPA optimization.

Experience

• 3+ years of experience in Physical Design
• Experience in advanced-node technologies is preferred
• Experience with block-level and/or top-level implementation

Key Responsibilities

• Execute the complete RTL-to-GDSII physical design flow.
• Perform Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Perform timing analysis and closure using STA.
• Debug and resolve setup/hold violations.
• Optimize designs for Power, Performance, and Area (PPA).
• Perform congestion analysis and optimization.
• Work on clock tree synthesis and clock optimization.
• Analyze and resolve DRC, LVS, antenna, and other physical violations.
• Perform physical ECOs and timing ECOs.
• Work closely with RTL, Synthesis, STA, and PV teams.
• Support block-level integration and tape-out activities.

Most Important Technical Skills

• RTL-to-GDSII Flow
• Floorplanning
• Power Planning
• Placement Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• Static Timing Analysis (STA)
• Setup/Hold Analysis
• Congestion Optimization
• Physical ECO
• DRC / LVS / Antenna
• IR Drop / EM awareness
• Signal Integrity
• PPA Optimization
• Advanced Node Physical Design

Tools

• Cadence Innovus
• Synopsys ICC2 / Fusion Compiler
• Synopsys PrimeTime
• Cadence Tempus
• Calibre
• RedHawk / Voltus

Education

• B.E./B.Tech/M.E./M.Tech in Electronics & Communication Engineering (ECE), Electrical & Electronics Engineering (EEE), Electronics Engineering, VLSI, or a related field.
• Strong academic background in VLSI, Digital Electronics, CMOS, and Semiconductor Design is preferred.