Physical Design Engineer

• Take complete ownership for implementation of Block level designs
• Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 16nm nodes or below
• Must have participated in all stages of the design (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM)
• Well versed with the Level timing closure (STA), Timing closure methodologies
• Role involves tasks in estimating power using industry standard tool,designing power grid , analyze power grid, doing static IR drop, dynamic IR drop
• Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification
• Working on very leading technology nodes: 16nm, 14nm, 10nm, 7nm
• Well aware of place and route methodologies and hands on experience with timing convergence
• Good communication skill to negotiate with top level for convergence

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