Physical Design Engineer- Static Timing Analysis (STA)

Introduction

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security, and scalability that clients and industries depend on every day. Working in Infrastructure & Technology means tackling complex challenges with curiosity and collaboration. You'll work with diverse technologies and colleagues worldwide to deliver resilient, future-ready solutions that power innovation. With continuous learning, career growth, and a supportive culture, IBM provides the opportunities to build expertise and shape the infrastructure that drives progress.

Your Role And Responsibilities

We are looking for a highly skilled Physical Design Engineer with deep expertise in static timing analysis using Cadence Tempus. The ideal candidate will own timing closure across multiple blocks and top-level designs, working closely with synthesis, PD, and signoff teams to achieve high-performance, low-power SoC designs. KEY RESPONSIBILITIES: Lead timing closure strategy for full-chip / hierarchical SoC designs using ILM/ETM-based flows Own signoff correlation between Tempus and other tools (PrimeTime, Innovus, etc.) Drive timing closure across all PVT corners and MMMC modes; debug and resolve timing violations Define and enforce timing methodology guidelines across the team; mentor junior/mid-level engineers Develop and validate SDC constraints; perform timing ECOs (buffering, resizing, logic restructuring) Drive automation – develop reusable TCL/Python scripts for timing analysis, reporting, and waiver management Analyze SI, crosstalk, and noise issues; handle Tempus SI for crosstalk delta-delay and glitch analysis Interface with Cadence EDA vendor for tool issues and new feature adoption Participate in architecture and floorplan reviews to identify timing risks early Contribute to DFM and low-power (CPF/UPF) timing signoff; generate timing reports and signoff closure

Preferred Education

Bachelor's Degree

Required Technical And Professional Expertise

Cadence Tempus (hands-on) Strong STA fundamentals MMMC / OCV / AOCV / POCV SDC expertise Timing ECO methodology ILM / ETM / QRC models SPEF correlation & back-annotation Tempus SI (crosstalk / glitch) CTS timing implications Multi-Vt / voltage island timing Innovus–Tempus in-design timing Cadence Conformal ECO Unix / Linux & TCL / Python scripting Advanced nodes (12nm or below) Physical-aware Tempus experience

Preferred Technical And Professional Experience

Preferred Professional and Technical Expertise Experience with Cadence Innovus or other PD tools Understanding of IR/EM and power analysis impacts on timing Familiarity with low-power design techniques (UPF/CPF) Exposure to signoff methodologies and tapeout cycles Knowledge of automation and timing flow optimization