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    Job · 18992424

    Qualcomm logo

    Physical Design Engineer, Sr Lead

    Qualcomm · Bengaluru · onsite · Posted 28d ago

    Undisclosed6–11 yrsfulltimeSourced fromNaukri

    About a minute. You'll make an account on the way through.

    About this role

    Job Summary
    As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
    Qualcomm Bangalore Camera Team is focused on developing high-performance, power-efficient, and highly optimized cores. In this role, you will drive end-to-end ownership of complex hierarchical modules, taking designs from RTL to GDSII, including synthesis, place route, and timing closure, with a strong emphasis on achieving best-in-class PPA (Power, Performance, Area).
    You will play a key role in delivering designs that push the boundaries of performance, efficiency, and scalability.
    We foster a collaborative, creative, and flexible work environment, united by a shared vision to build innovative methods that have a meaningful impact.
    Minimum Qualifications
    • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
    • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
    • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
    • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
    • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
    • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
    Experience
    • 6+ years of experience in Physical Design, including floorplanning, Place Route (PNR), Clock Tree Synthesis (CTS), and STA signoff checks
    • Hands-on experience owning end-to-end Physical Design from netlist to GDSII, including HM-level PV, LEC, low-power checks, PDN design, and STA closure
    • Experience with voltage islands and low-power design methodologies, flows, and implementation
    • Strong focus on achieving optimal PPA (Power, Performance, Area)
    • Strong familiarity with industry-standard tools such as Fusion Compiler (FC), Genus, Innovus, PrimeTime (PT), Tempus, Voltus, and RedHawk
    • Solid understanding of the full Physical Design flow from floorplanning to post-route optimization and timing signoff, including IR drop analysis and physical verification
    • Experience in implementing complex ECOs for timing convergence across multiple corners using Tweaker, Tempus, and physical ECO flows in PrimeTime
    • Knowledge of power optimization techniques and methods to minimize power consumption
    • Experience in deep submicron technology nodes (preferred)
    • Understanding of high-performance and low-power implementation techniques (preferred)
    • Strong fundamentals in Physical Design and VLSI concepts
    • Proficiency in scripting languages such as Perl, Python and TCL
    Roles and Responsibilities
    • Collaborate with cross-functional teams (Design, CAD) to address critical physical design challenges in Camera PNR Implementation.
    • Develop innovative techniques within Physical Design and optimization space to meet stringent PPA targets.
    • Engage with external CAD tool vendors and internal CAD teams to identify and enhance optimization issues related to Camera designs.
    • Partner with all block-level implementation teams to analyze, implement, and improve optimization methods relevant to the designs.

    Sourced from naukri

    Skills

    PrimetimeHardware Engineeringphysical designmechanical systemsInnovuscompileroptimization techniquesAnalogPVPerlCADElectronics EngineeringLow-Power DesignClock Tree SynthesisDigital TransformationPhysical Verification

    About Qualcomm

    Qualcomm logo

    Qualcomm

    Semiconductors

    22k+

    employees

    1996

    30 years old

    San Diego,California

    United States

    About

    Qualcomm invents breakthrough technologies that transform how the world connects, computes and communicates.

    Industries

    SemiconductorsHardware & Networking

    Employee ratings

    1,207 reviews

    3.7/ 5

    Culture

    3.4

    Career growth

    3.2

    Work-life

    3.3

    Employees rate it well for

    Work Life Balance267Salary160Work Culture155Learning100Senior Management91

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