PD PNR Engineer

Responsible for end-to-end physical implementation and convergence of complex SoC/IP tiles. The engineer will drive floorplanning, place-and-route, timing closure, power and area optimization, physical verification readiness, and ECO implementation while collaborating closely with RTL, architecture, CAD, timing, clocking, and full-chip teams. Expected to independently own critical tiles, deliver high-quality milestones, and contribute to methodology and automation improvements.