PD Engineer

IR/EM Lead Job Summary

The IR/EM Lead will drive reliability signoff and closure for advanced SoC and IP designs, ensuring robust power delivery and electromigration compliance across all project phases. This role requires deep expertise in power integrity, IR drop analysis, electromigration verification, methodology development, and cross-functional technical leadership to enable successful tapeouts at advanced process technologies.

Key Responsibilities

• Lead all IR/EM activities for complex SoC and IP programs from floorplan through tapeout.
• Define and drive project-wide IR/EM closure strategies, schedules, and signoff criteria.
• Perform and review static and dynamic IR-drop analysis across full-chip and block-level designs.
• Lead electromigration analysis and closure for power grids, clock networks, signal routing, and package interfaces.
• Collaborate closely with Physical Design, Package Design, Power Architecture, Clock, RTL, CAD, and Technology teams.
• Identify power integrity risks early and drive mitigation plans through implementation and signoff stages.
• Develop and deploy methodologies, automation, dashboards, and best practices to improve IR/EM convergence.
• Guide teams in power grid architecture, decap planning, bump assignment, power distribution optimization, and reliability improvements.
• Drive technical reviews and communicate design health, risks, and recommendations to project leadership.
• Mentor engineers and provide technical leadership across multiple projects.

Technical Requirements

• Strong expertise in Power Integrity and Electromigration analysis methodologies.
• Deep understanding of:
  • Static and Dynamic IR Analysis
  • Electromigration Verification
  • Power Grid Design and Optimization
  • Decap Planning and Analysis
  • Voltage Drop Debug and Closure
  • Advanced Node Reliability Requirements
• Hands-on experience with industry-standard IR/EM signoff tools.
• Strong scripting and automation skills (Python, Tcl, Perl, or similar).
• Strong understanding of advanced-node physical design implementation flows.

Leadership Expectations

• Act as the primary technical owner for IR/EM signoff and closure.
• Drive technical decisions impacting product reliability and design quality.
• Influence implementation methodology across project and organizational boundaries.
• Lead root-cause analysis for power integrity issues and drive systematic improvements.
• Coach engineers and establish technical best practices for reliability signoff.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related discipline.
• Typically 5-15 years of experience in Physical Design, Power Integrity, Reliability Analysis, or Signoff Engineering.
• Proven experience leading IR/EM closure for large SoC designs through successful tapeout.

Preferred Qualifications

• Experience with 5nm, 4nm, 3nm, or newer process technologies.
• Understanding of package and system-level power delivery networks.
• Familiarity with thermal analysis and reliability methodologies.
• Experience developing automation and signoff productivity frameworks.
• Strong communication and project leadership skills.

Success Metrics

• First-pass IR/EM signoff readiness.
• Timely closure of power integrity and reliability issues.
• Improved methodology efficiency and signoff turnaround time.
• Reduced late-stage design risk and tapeout escapes.
• Effective mentorship and technical leadership across the organization.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.