PD Engineer

The Job Role:

We are looking for experienced Physical Design Engineers specializing in Place and Route (PNR) for advanced technology nodes of 3nm and below. The ideal candidate should have strong expertise in physical implementation, timing closure, power optimization, and physical design sign-off for complex SoC designs.

• Perform end-to-end physical design implementation, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Drive timing closure and optimize setup/hold violations for advanced-node designs.
• Perform physical design optimization for Power, Performance, and Area (PPA).
• Work on congestion analysis, signal integrity, crosstalk, and routing optimization.
• Analyze and resolve design rule violations (DRCs) and electrical violations.
• Perform post-route optimization and timing closure across multiple process, voltage, and temperature (PVT) corners.
• Collaborate with RTL, synthesis, STA, DFT, and methodology teams to achieve design sign-off.
• Work with advanced-node process constraints, including complex design rules and interconnect challenges.
• Ensure successful physical design sign-off through timing, power, and physical verification checks.

• Strong experience in Place and Route (PNR) for advanced technology nodes, specifically 3nm, 2nm, or below.
• Expertise in floorplanning, placement, CTS, routing, and post-route optimization.
• Strong understanding of Static Timing Analysis (STA), timing constraints, and multi-corner multi-mode (MCMM) analysis.
• Hands-on experience with industry-standard EDA tools such as Synopsys IC Compiler II (ICC2), Fusion Compiler, or Cadence Innovus.
• Experience with extraction and timing analysis tools such as PrimeTime or Tempus.
• Knowledge of physical verification, DRC, LVS, IR drop, and electromigration (EM).
• Strong understanding of low-power design techniques, congestion management, and signal integrity.
• Experience working on complex SoC, CPU, GPU, networking, or high-performance computing designs is an advantage.