PD CAD Engineer, Senior

Company: Qualcomm India Private Limited

Job Area: Engineering Group, Engineering Group > Hardware Engineering

General Summary:

• Drive the Physical Design lifecycle of chip development with a strong focus on Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Physical Signoff.
• Own and execute block-level and SoC-level floorplanning activities using Cadence Innovus, including:

• Macro planning and placement
• Power planning (rings, straps, grids)
• Pin assignment and I/O planning
• Floorplan optimization for PPA (Power, Performance, Area)
• Congestion and routability analysis
• Hierarchical integration and partitioning strategies

• Perform hands-on Physical Design implementation and drive PPA improvements through floorplan and implementation optimizations.

• Develop deep understanding of process technologies and Physical Design methodologies and contribute to flow enablement for advanced technology nodes.

• Provide tool support, debugging, and methodology guidance to Physical Design engineers across global teams.

• Develop and maintain automation, productivity enhancements, and third-party tool integrations using Tcl/Python.

• Strong hands-on expertise in Floorplanning using Cadence Innovus is mandatory.

• Proven experience in:
• Block/Subsystem/SoC floorplanning
• Macro placement optimization
• Power planning and grid design
• Pin assignment and I/O planning
• Congestion analysis and mitigation
• Physical hierarchy and partitioning
• Floorplan-driven PPA optimization

• Strong understanding of complete Physical Design flows using Innovus, Fusion Compiler FC, ICC2, or equivalent PR tools.
• Hands-on scripting proficiency in Python, Tcl, and/or C++.
• Good understanding of advanced-node implementation challenges and Physical Design methodologies.
• Ability to quickly learn new technologies, work effectively in cross-functional teams, and communicate technical concepts clearly.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Experience

• 35 years of hands-on Physical Design experience, with significant exposure to floorplanning and implementation using Cadence Innovus.
• Experience in advanced technology node designs and full-chip/block-level physical implementation is highly desirable.
• Demonstrated experience in floorplan convergence, congestion closure, timing closure, and power-aware design implementation.

Preferred/Niche Skills

Handling support tools like Encounter/Innovus/edi/fc/Icc2 (or other equivalent PNR tool). One or more of the above is mandatory*