PD CAD Engineer, Senior

• Drive thePhysical Design lifecycle of chip development with a strong focus onFloorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Physical Signoff.
• Own and executeblock-level and SoC-level floorplanning activities using Cadence Innovus, including:
  • Macro planning and placement
  • Power planning (rings, straps, grids)
  • Pin assignment and I/O planning
  • Floorplan optimization for PPA (Power, Performance, Area)
  • Congestion and routability analysis
  • Hierarchical integration and partitioning strategies
• Perform hands-on Physical Design implementation and drivePPA improvements through floorplan and implementation optimizations.
• Develop deep understanding of process technologies and Physical Design methodologies and contribute to flow enablement for advanced technology nodes.
• Provide tool support, debugging, and methodology guidance to Physical Design engineers across global teams.
• Develop and maintain automation, productivity enhancements, and third-party tool integrations using Tcl/Python.

• Strong hands-on expertise in Floorplanning using Cadence Innovus is mandatory.
• Proven experience in:
  • Block/Subsystem/SoC floorplanning
  • Macro placement optimization
  • Power planning and grid design
  • Pin and interface planning
  • Congestion analysis and mitigation
  • Physical hierarchy and partitioning
  • Floorplan-driven PPA optimization
• Strong understanding of complete Physical Design flows usingInnovus, Fusion Compiler (FC), ICC2, or equivalent PR tools.
• Hands-on scripting proficiency inPython, Tcl, and/or C++.
• Good understanding of advanced-node implementation challenges and Physical Design methodologies.
• Ability to quickly learn new technologies, work effectively in cross-functional teams, and communicate technical concepts clearly.

Bachelor''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORMaster''s degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

• 3-5 years of hands-on Physical Design experience, with significant exposure tofloorplanning and implementation using Cadence Innovus.
• Experience in advanced technology node designs and full-chip/block-level physical implementation is highly desirable.
• Demonstrated experience in floorplan convergence, congestion closure, timing closure, and power-aware design implementation.