Mixed-Signal Co-Simulation Engineer
Wells Fargo · Hyderabad · onsite · Posted 21d ago
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About this role
Position: Mixed-Signal Co-Simulation Engineer (BB46FT RM 4457)
Key Responsibilities
Key Responsibilities
- Run full-chip or block-level mixed-signal co-simulations using Cadence AMS Designer/Xcelium or Synopsys VCS.
- Develop behavioral analog models using Verilog-AMS, Verilog, and SystemVerilog Real Number Modeling (RNM/wreal).
- Build metric-driven verification environments using SystemVerilog and UVM-AMS.
- Debug analog and digital interface issues, waveform anomalies, simulation convergence failures, and drive functional coverage closure.
- Develop automation scripts in Python, Perl, or Tcl for verification flows, regression management, and reporting.
- Create and execute verification plans to validate behavioral models against transistor-level schematics.
- Configure and execute mixed-mode simulations with selected blocks running at schematic/SPICE level while the remaining design uses behavioral models.
- SystemVerilog, UVM, Verilog, Verilog-AMS, and SystemVerilog RNM (wreal)
- Mixed-signal verification and co-simulation experience
- Knowledge of PLL, DLL, DCC, ADC, DAC, LDO, Bandgap, and ZQ Calibration
- Experience with Cadence Virtuoso, Spectre, Xcelium, Cadence AMS Designer, or Synopsys VCS
- Strong hands-on experience in mixed-signal/AMS verification.
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Skills
SystemVerilog RNM wrealautomation scripts in Pythontclcadence virtuosoPerlVerilogUVMSystem VerilogXceliumSpectreSynopsys VCSco-simulationVerilog-AMSCadence AMS Designermixed signal verification
About Wells Fargo
Wells Fargo
Financial Services
20k+
employees
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174 years old
Bengaluru/Bangalore, Karnataka
India
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Wells Fargo works to create positive social impact in the communities it serves by supporting housing affordability, small business growth, financial health, and a low-carbon economy.
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