HYDERABAD · FULLTIME
Mixed-Signal Co-Simulation Engineer (BB46FT RM 4457)
Sourceright Technologies
Hyderabad · onsite · Posted 12d ago
Sourced from
Undisclosed4–6 yrsfulltimeHyderabad
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Section · 01
About this role
Position: Mixed-Signal Co-Simulation Engineer (BB46FT RM 4457)
Key Responsibilities
- Run full-chip or block-level mixed-signal co-simulations using Cadence AMS Designer/Xcelium or Synopsys VCS.
- Develop behavioral analog models using Verilog-AMS, Verilog, and SystemVerilog Real Number Modeling (RNM/wreal).
- Build metric-driven verification environments using SystemVerilog and UVM-AMS.
- Debug analog and digital interface issues, waveform anomalies, simulation convergence failures, and drive functional coverage closure.
- Develop automation scripts in Python, Perl, or Tcl for verification flows, regression management, and reporting.
- Create and execute verification plans to validate behavioral models against transistor-level schematics.
- Configure and execute mixed-mode simulations with selected blocks running at schematic/SPICE level while the remaining design uses behavioral models.
Required Skills and Qualifications
- SystemVerilog, UVM, Verilog, Verilog-AMS, and SystemVerilog RNM (wreal)
- Mixed-signal verification and co-simulation experience
- Knowledge of PLL, DLL, DCC, ADC, DAC, LDO, Bandgap, and ZQ Calibration
- Experience with Cadence Virtuoso, Spectre, Xcelium, Cadence AMS Designer, or Synopsys VCS
- Strong hands-on experience in mixed-signal/AMS verification.
Job Category: Others
Job Type: Full Time
Job Location: Bangalore Hyderabad
Experience: 4-6 years
Notice period: 0-30 days
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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Section · 02
Skills
AutomationCadenceVirtuosocadence virtuosoregressionAnalogPerlVerilogUVMsynopsysDebugPythonSchematics