Memory Layout Engineer

Job Title: Memory Layout Engineer

Job Location: Bengaluru (Onsite)

Experience: 4 - 10 Years of Experience

Notice Period: Immediate - 15 Days

Key Skills & Responsibilities:

• Hands-on experience in layout of memory blocks like control logic, sense amplifiers, I/O blocks, bit cell array, decoders, etc.
• Strong experience in SRAM/DRAM, memory compiler IPs, and memory periphery circuits
• Expertise in top-level memory integration, DRC, LVS, density verification, and physical closure
• Understanding of IR/EM challenges in memory layouts
• Proficiency with Cadence/Synopsys tools for layout and Mentor/Cadence/Synopsys tools for physical verification
• Exposure to ultra-deep sub-micron design challenges and DFM guidelines
• Knowledge of memory architecture, bitcell layout concepts, and FinFET design rules
• Ability to optimize layout for area, power, speed, yield, and manufacturability
• Collaboration with circuit design, verification, PDK, and methodology teams