Memory Layout Design Engineer

Required Technical Skills

23 years of hands-on experience in SRAM or custom memory layout.

Strong understanding of CMOS fundamentals and SRAM architectures.

Experience with 6T, 8T, or pseudo-8T SRAM bit cells.

Practical knowledge of floorplanning, device placement, routing, and layout optimization.

Experience with memory blocks such as:

Bit-cell arrays

XDEC/YDEC

Control and I/O blocks

Sense amplifiers

Pre-charge and write-driver circuits

Clock-generation and self-timing circuits

Strong experience in DRC and LVS debugging.

Familiarity with advanced and mature technology nodes.

Understanding of layout-dependent effects, matching, parasitics, and signal integrity.

Ability to interpret circuit schematics and debug physical-verification results.

Tools

Experience with one or more of the following:

Cadence Virtuoso

Synopsys Custom Compiler

Siemens Calibre

Synopsys ICV

HSPICE or equivalent circuit-simulation tools

Preferred Skills

Experience with SRAM timing, power, stability, and noise-margin analysis.

Knowledge of PVT analysis and memory marginality.

Familiarity with sense-amplifier offset analysis.

Exposure to advanced nodes such as 2nm, 3nm, 5nm, or 7nm.

Basic Python or scripting experience for netlist generation and automation.

Experience taking memory blocks through complete DRC/LVS closure.