Memory Layout Design ( ASIC ) Engineer

Company: Vicharak

Location: Surat, Gujarat

Employment: Full-time

Experience: 6+ years in custom IC layout, preferably with memory layout experience

Vicharak builds edge computing platforms and is developing ASICs for energy-efficient AI processing. Our semiconductor work spans custom memory, compute-in-memory architectures and highly parallel compute engines.

We are looking for a Memory Layout Engineer to turn transistor-level memory designs into compact, robust and manufacturable layouts. You will work closely with circuit designers and physical design engineers, contributing from bitcell development through macro integration and tapeout.

• Design and optimize custom memory bitcells, arrays and peripheral circuits, including SRAM memory.
• Develop layouts for decoders, wordline drivers, precharge circuits, sense amplifiers, write drivers and refresh circuitry.
• Optimize cell area, array pitch, routing and parasitics while meeting foundry design rules and circuit requirements.
• Build repeatable array structures with appropriate boundary cells, dummy structures, well ties and power distribution.
• Run and debug DRC, LVS and parasitic extraction at cell, block and macro levels.
• Work with circuit designers to resolve post-layout timing, power, read/write margin and retention issues.
• Address matching, coupling, electromigration, IR drop and layout-dependent effects.
• Prepare verified layout deliverables, GDS/OASIS and integration views for the SoC team.
• Support foundry reviews, design-rule clarifications and tapeout signoff.
• Automate repetitive layout generation and verification tasks.

• Hands-on experience in full-custom transistor-level IC layout.
• Experience with memory bitcells, memory arrays or memory peripheral circuits.
• Proficiency with Cadence Virtuoso or an equivalent custom layout environment.
• Experience with physical verification and extraction tools such as Calibre, Pegasus, PVS or Quantus.
• Ability to read transistor-level schematics and understand how layout affects circuit behaviour.
• Strong understanding of CMOS layout, device placement, well structures, contacts, vias and interconnect.
• Practical experience debugging DRC and LVS errors and working with foundry PDKs.
• Understanding of parasitic resistance, capacitance and their impact on memory performance.
• B.E./B.Tech./M.E./M.Tech. in Electronics, Electrical Engineering, VLSI or a related field, or equivalent practical experience.

• Experience with FinFET processes and advanced-node layout constraints.
• Familiarity with low-voltage memory design, retention-sensitive nodes and read/write assist circuits.
• Experience taking custom memory blocks through tapeout and supporting silicon debug.
• Familiarity with SKILL, Python or Tcl for layout automation.
• Experience creating LEF abstracts and coordinating memory macro integration with physical design teams.

You will help take custom memory blocks from schematics to verified, tapeout-ready layouts. Success means compact layouts, reliable verification closure, controlled parasitics and clean integration into the larger ASIC.

• Work on custom memory and AI silicon with direct influence on design decisions.
• Own technically challenging blocks from early development through tapeout.
• Collaborate closely with a growing semiconductor team.
• Build technology for an Indian company developing its own computing platforms.

• Share your resume and a brief summary of the memory or custom layout blocks you have worked on, including process nodes, tools used and your contribution to verification or tapeout. Please exclude confidential information from previous employers.