Memory Layout and IO Layout Engineer

Position 1: IO Layout Design Engineer: Min 4+ yrs of experience required.

Roles & Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc., Need knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E3nm, , 5nm etc., 

SKILL: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc. Should possess good knowledge on CMOS functionality, CMOS fabrication process, foundries and challenges in latest technology nodes. 

Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required. 

Joining date: 2 - 4 Weeks 

Position 2: Memory Layout:  Min 3+ yrs of experience required.

Role: Layout Design of SRAM/CAM/RF compiler memories in 2/3/4/5nm technology. 

Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom memories. 

Skills : Well experienced in using industry standard EDA tools like Cadence Virtuoso, Mentor Graphics Caliber etc. Good problem solving and logical reasoning skills. Good communication skills required 

Understanding of memory architecture

Experience in creating basic memory layouts from scratch

Knowledge of memory peripheral blocks, including control blocks, I/O blocks, and row drivers

Additionally, they are seeking expertise in:

Knowledge of compiler issues

Understanding of reliability issues

Simulation effects

EMI (Electromagnetic Interference) considerations

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