Memory Design Engineer

Position: Memory Design & Layout Engineer

Experience: 5+ Years

Job Responsibilities:

* Design and develop memory circuits and custom memory macros based on product and technology requirements.

* Work on SRAM, ROM, Register File and other memory architectures.

* Perform transistor-level circuit design, simulation and optimization of memory blocks.

* Develop custom memory layouts based on circuit schematics and design requirements.

* Handle floorplanning, device placement, routing, matching and area optimization.

* Work closely with Memory Design, Layout, Physical Verification, PDK and Technology teams.

* Perform and debug DRC, LVS, ERC and PEX checks.

* Analyze timing, power, area, noise, leakage and parasitic effects and optimize the design.

* Support post-layout simulation and characterization of memory macros.

* Participate in design reviews and contribute to memory architecture and implementation methodologies.

* Ensure designs meet foundry/PDK design rules, reliability and yield requirements.

Required Skills:

* 5+ years of experience in Memory Design / Custom Layout / Memory IP development.

* Strong understanding of CMOS circuit design and memory architectures.

* Hands-on experience with SRAM/ROM/Memory macros is preferred.

* Experience with Cadence Virtuoso and related circuit/layout tools.

* Good knowledge of SPICE simulation and transistor-level circuit analysis.

* Experience with DRC, LVS, ERC and PEX.

* Strong understanding of layout techniques, matching, symmetry, common-centroid, shielding and parasitic optimization.

* Understanding of memory timing, power, leakage and stability considerations.

* Good debugging and problem-solving skills.