Low Power Design Engineer (RTL)

The Role

The focus of this role is to plan, build, design/integration of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design.

The Person

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Key Responsibilities

• Define SoC and subsystem power architecture.
• Develop and maintain power intent using UPF/CPF methodologies.
• Implement low-power techniques such as:
  • Power gating
  • Clock gating
  • Multi-voltage domains
  • Dynamic Voltage and Frequency Scaling (DVFS)
  • Retention and isolation strategies
• Collaborate with RTL designers to integrate low-power features.
• Run and debug low-power checks using EDA tools.
• Perform power estimation, analysis, and optimization throughout the design cycle.
• Drive power signoff activities and ensure compliance with project power budgets.
• Support functional verification teams in low-power verification planning and execution.

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.