Lead Physical Verification Engineer

Lead Physical Verification Engineer

Location: Chennai

Experience: 6+ Years

Job Description:

We are looking for an experienced Lead Physical Verification Engineer with strong expertise in physical verification and hands-on experience with Cadence tools to drive PV activities for advanced semiconductor designs.

Key Responsibilities:

• Lead physical verification activities, including DRC, LVS, ERC, and Antenna checks.
• Perform full-chip physical verification and debug complex verification violations.
• Work on block-level and top-level physical verification sign-off.
• Collaborate with Physical Design, Analog Layout, and Foundry teams to resolve verification issues.
• Drive verification closure, sign-off readiness, and quality improvements.
• Support and guide team members in physical verification methodologies.

Must-Have Skills:

• 6+ years of experience in Physical Verification.
• Strong hands-on experience with Cadence tools.
• Expertise in DRC, LVS, ERC, and Antenna checks.
• Experience in full-chip and block-level physical verification sign-off.
• Strong debugging skills and knowledge of physical verification flows.
• Good understanding of CMOS layout and foundry sign-off requirements.

Preferred Skills:

• Experience with advanced technology nodes.
• Scripting knowledge in Tcl, Python, or Unix Shell.
• Prior experience in leading or mentoring physical verification teams.