Lead Physical Design Engineer

Job Summary


Key Responsibilities

• Work with the customer, SOC architects, the CAD team and the design team and drive physical design flows for best-in-class ASIC solutions
• Implementing RTL to GDS2 flow
• Handling Floorplan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR, Formal Equivalence
• Deft at Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus.
• Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off
• Identify complex technical problems, break them down, summarize multiple possible solutions,
• Drive and hands-on flow development and scripting

Preferred Experience

• 7+years of professional experience in physical design, preferably with high-performance designs.
• Experience in automated synthesis and timing driven place and route of RTL blocks for high-speed data path and control logic applications.
• Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.
• Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery
• Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation
• Versatility with scripts to automate design flow.
• Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
• Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm
• Excellent physical design and timing background.
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details

Academic Credentials

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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