Lead Physical Design Engineer

Company Description Quest Global is an engineering solutions company with over 25 years of experience solving complex problems by combining advanced technology and deep industry expertise. The organization supports customers across diverse sectors, including Aerospace & Defense, Automotive, Energy, Hi-Tech, MedTech & Healthcare, Rail, and Semiconductor. Quest Global operates in more than 20 countries, with 96 delivery centers and over 23,000 team members worldwide, offering global exposure and collaboration opportunities. The company is committed to integrity in its recruitment processes and never requests payment at any stage of hiring. Candidates can learn more about Quest Global and its career opportunities on the corporate and careers websites.
Role Description This full-time Lead Physical Design Engineer role is a hybrid position based in Bengaluru South, with flexibility for partial work from home. The role involves leading end-to-end physical design activities, including floorplanning, placement, clock tree synthesis, routing, and timing closure for complex SoCs and ASICs. The Lead Engineer will collaborate closely with logic, RTL, and circuit design teams to ensure seamless integration, optimal performance, and adherence to power, area, and reliability targets. Daily responsibilities include overseeing physical verification, driving sign-off, resolving design and implementation issues, and mentoring team members on best practices and methodologies. The role also requires coordinating with cross-functional stakeholders, supporting project planning, and contributing to continuous improvement of design flows and tools.
Qualifications

• Strong expertise in Physical Design, including floorplanning, placement, CTS, routing, and timing closure.
• Proficiency in Physical Verification methodologies such as DRC, LVS, ERC, and integration of sign-off checks.
• Solid understanding of Logic Design and Circuit Design principles, including performance, power, and area trade-offs.
• Hands-on experience with RTL Design, RTL-to-GDS flows, and collaboration with front-end design teams.
• Experience with standard EDA tools for physical implementation and verification (e.g., Cadence, Synopsys, Siemens tools or similar).
• Ability to lead and mentor engineering teams, manage deliverables, and drive technical decisions.
• Effective communication and collaboration skills for working in cross-functional, global teams.
• Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, or a related field.
• Prior experience in semiconductor or SoC/ASIC design projects at advanced technology nodes is highly beneficial.