Lead PDN EMIR Engineer

Required Qualifications B.Tech/M.Tech in Electronics, Electrical Engineering, VLSI, or related field. 8+ years of experience in Physical Design, Power Integrity, or Signoff.

Key Responsibilities Technical Skills: Own full-chip and subsystem-level PDN signoff for complex SoCs. Define PDN signoff criteria across project milestones. Drive power integrity closure for functional, DFT, LBIST, capture, and stress modes. Lead package-aware IR/EM analysis and chip-package co-optimization. Define and review power grid architecture, bump planning, power switch strategy, and decap methodology. Drive Vmin, peak EM, dynamic IR, and thermal-aware analysis. Methodology & Innovation Develop next-generation PDN signoff methodologies. Automate PDN flows using TCL/Python/Shell. Improve runtime, capacity, dashboarding, and regression infrastructure. Collaborate with EDA vendors (Ansys/Cadence/Synopsys) for feature enhancements and tool debug. Establish best practices and reusable signoff frameworks across projects. Cross-Functional Collaboration Work closely with Physical Design teams to drive PDN-aware floorplanning, placement, routing, and ECO solutions. Partner with DFT teams to optimize pattern power and capture-mode reliability. Collaborate with Package and Thermal teams on package RLC optimization and thermal correlation. Support silicon bring-up, debug, and correlation of pre-silicon versus post-silicon measurements. Project Execution Provide technical risk assessment and mitigation plans. Drive closure of critical PDN hotspots with minimal PPA impact. Present signoff status to management and project stakeholders. Ensure on-time delivery for tapeout milestones. Lead reviews for high-risk blocks and top-level integrations. People Leadership Mentor engineers and PDN owners across multiple projects. Define training content and technical roadmaps for the team. Lead technical reviews and establish signoff governance. Influence organizational PDN strategy and future technology direction.

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