Lead - Formal Verification Engineer

• Define formal verification strategy and signoff methodology for SoCs
• Own SoC-level LEC signoff from RTL to final netlist
• Resolve complex, late-stage equivalence failures across hierarchies and power domains
• Drive best practices, reusable FV flows, and signoff checklists
• Mentor formal verification engineers and review signoff quality
• Interface with customers, internal signoff teams, and EDA vendors

Tools & Skills

• Formal Verification: Synopsys Formality, Cadence Conformal (LEC / Low Power)
• HDL: Verilog, SystemVerilog
• Low Power: UPF-aware formal verification
• DFT Awareness: Scan logic, clock-gating, test logic
• Understanding of synthesis, STA, and physical transformations
• Scripting: Tcl (mandatory), Shell / Python (preferred)