Lead Engineer - Design Verification (Low power UPF/CPF)

Job Summary

In this role, you will work on low-power design verification for complex SoCs, ensuring robust and power-efficient silicon. You will focus on validating power intent and low-power features using UPF/CPF methodologies across the design lifecycle.

The Design Verification team collaborates closely with RTL, architecture, and physical design teams to deliver high-quality silicon. We focus on coverage-driven verification and advanced low-power methodologies.

Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making.

Responsibilities

• Understand and verify power domains and power intent (UPF/CPF)
• Develop and execute test plans for low-power modes and states
• Own end-to-end DV: testbench development, testcases, assertions, debugging (RTL/UPF)
• Drive functional and assertion coverage closure
• Build and enhance SystemVerilog/UVM verification environments
• Perform power-aware verification and debug complex issues
• Collaborate with cross-functional teams and explore advanced DV methodologies

Requirements

• BS/MS in Electrical or Computer Engineering (or related field)
• 6-8 years of experience in design verification
• Strong SystemVerilog/UVM skills
• Experience with assertion-based and coverage-driven verification
• Solid understanding of low-power design techniques
• Experience with UPF/CPF-based verification
• Knowledge of low-power SoC constructs (clock gating, isolation, level shifters, retention)
• Strong debugging and problem-solving skills

Nice to Have

• Experience with formal/static verification
• Familiarity with Synopsys NLP tools
• Knowledge of GLS / PA-GLS
• Scripting skills (Python/Perl)
• Experience with ASIC tools and flows

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