BENGALURU · FULLTIME
Lead Emulation Engineer
Aster Labs
Bengaluru · onsite · Posted 51d ago
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Section · 01
About this role
Job Summary
We are looking for a Lead Emulation Engineer to lead the deployment and execution of complex SoC/IP verification on hardware emulation platforms. The candidate will work closely with design verification, RTL, architecture, firmware, and post-silicon teams to accelerate functional verification, software development, performance validation, and system-level debug.
Experience
Experience - 6-10 years
Responsibilities
- Lead emulation strategy and execution for complex SoC/IP designs.
- Develop and maintain emulation environments for large-scale ASIC/SoC designs.
- Bring up RTL designs on emulation platforms and debug compilation, mapping, and runtime issues.
- Develop and execute emulation-based verification plans.
- Enable software and firmware teams to execute workloads on emulated hardware.
- Support early software bring-up and system-level validation.
- Develop transactors, monitors, BFMs, and other emulation components as required.
- Optimize emulation builds for performance, capacity, and compile/runtime efficiency.
- Debug functional issues across RTL, testbench, emulation environment, and software.
- Work closely with DV teams to migrate suitable simulation-based tests to emulation.
- Develop automation for test execution, regression, data collection, and debug.
- Analyze emulation failures and drive root-cause identification with RTL/DV teams.
- Support performance and stress testing using realistic system workloads.
- Drive emulation methodology improvements and infrastructure enhancements.
- Mentor junior and senior emulation engineers.
- Provide technical leadership during major IP/SoC bring-up milestones.
- Support silicon bring-up by developing reusable emulation-based debug strategies.
Required Technical Skills
- ASIC/SoC emulation.
- Cadence Palladium.
- Synopsys ZeBu.
- SystemVerilog/Verilog.
- UVM-based verification environments and simulation-to-emulation flows.
- Emulation compile, mapping, partitioning, acceleration, and runtime concepts.
- Debugging and problem-solving skills.
- Python, Tcl, Perl, C/C++.
Preferred Experience
- Experience with large, complex SoCs and multi-IP environments.
- Experience with PCIe, UALink, CXL, Ethernet, NoC, memory systems, or other high-speed interfaces.
- Experience with software-driven validation and early firmware enablement.
- Experience developing custom transactors and acceleration models.
- Experience with performance benchmarking and system-level workload validation.
- Experience supporting pre-silicon and post-silicon debug.
Leadership Expectations
- Independently own emulation bring-up and execution for major IPs/subsystems.
- Lead technical discussions with DV, RTL, firmware, and architecture teams.
- Mentor engineers and improve emulation productivity.
- Drive issues to closure while working against aggressive project/tape-out schedules.
- Establish reusable emulation flows and best practices.
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
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Section · 02
Skills
Section · Company
About Aster Labs

Aster Labs
Bengaluru
IN
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