Lead DV Engineer ( DUTs in ARM architecture )
Proxelera · Bengaluru · onsite · Posted 29d ago
Undisclosed9–12 yrsfulltimeSourced from
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About this role
Job Title: Lead DV Engineer ( DUTs in ARM architecture ) - 9-12 Yrs
Location: Bangalore
No. Of positions: 3
Work Mode: 5 Days WFO
Experience required: 9-12 years
Interview Levels:
Interview Rounds: 2 rounds
Interview Preference: Virtual
Interview Rounds: 2 rounds
Interview Preference: Virtual
THE ROLE:
- As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs.
- As a member of the front-end design verification team, you will work closely with architecture, IP design and SOC verification engineers to achieve first pass silicon success.
The Person:
- The ideal candidate will have experience verifying RTL for IP or subsystems and understand architectural specifications.
- Responsibilities include IP and subsystem design verification and working collaboratively with the IP/SoC team.
Key Responsibilities:
- Verification of IP and subsystems for other 3rd party IPs.
- Create test plans, develop testbenches, write constrained random test cases, perform code coverage analysis, create coverpooints and analyze functional coverage.
ACADEMIC CREDENTIALS: - Bachelors or Masters degree in Computer Engineering/Electrical Engineering
Additional Notes:
- Candidates must demonstrate strong hands on experience in the listed skills, along with the ability to quickly understand project requirements and deliver results from day 1 in a fast paced environment.
- Work collaboratively with other members of the IP team to support design implementation for IP delivery to SOC
- Work in partnership with SOC teams to support the IP at SOC level, including SOC verification, performance testing, software, firmware, and post-silicon bring-up
Top Mandatory Skills:
- 9-12 years of full-time experience in design verification on DUTs in ARM architecture
- Previous working experience on design verification on ARM IPs, such as Cortex-A cores/DSU, Cortex-R cores/DSU, SMMU, CMN, GIC, Coresight, NIC/NOC, PCK, STM, etc.
- Proficiency in system Verilog, UVM, and C for digital design verification
- Code coverage analysis and how to close line, expression and branch coverage
- Experience with assertion-based verification (ABV)
- Detailed knowledge of how to code coverpoints and closing functional coverage in a constrained random environment
Nice to have Secondary Skills:
- DV lead role experience is a plus
- Ability to take on somewhat open-ended tasks, create concrete plan to execute and complete these tasks independently
- Ability to work with multi-level functional teams across various geographies
- Outstanding interaction skills while communicating both written and verbally
- Outstanding problem-solving and analytical skills
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
Sourced from naukri
Skills
Test CasesSOCanalytical thinkingarm architecturecomputer engineeringFirmwarecode coverageipsPerformance Testingdigital designNOCSystem VerilogSOC VerificationDesign Verificationelectrical engineeringGraphicsArchitecture
About Proxelera
Proxelera
IT Services & Consulting
51-200
employees
2021
5 years old
Bangalore / Bengaluru, Karnataka
India
₹12.6L PA avg
Avg at Proxelera
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Proxelera provides VLSI design expertise to global customers. Our differentiation is our quality, timeliness and cost-effectiveness
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