Lead Design Verification Engineer

What Youll Be Working On

• End-to-end ASIC/SoC Design Verification
• Building scalable UVM-based verification environments
• Developing test plans, test cases, assertions & functional coverage models
• Regression management and coverage closure
• Debugging complex issues using tools like Verdi / Sim Vision

Technical Expertise We’re Looking For

• Strong hands-on experience in Verilog / System Verilog
• Solid experience with UVM methodology
• C/C++, DPI integration knowledge
• Scripting skills in Python / Perl / Makefile
• Strong debugging and root-cause analysis skills
• Good understanding of SoC/ASIC design flow

Protocol Experience (Preferred)

• Hands-on experience in high-speed interfaces such as PCIe (Gen4/Gen5)
• Experience or exposure to UCIe (Universal Chiplet Interconnect Express) protocol
• Knowledge of AMBA USB, DDR, SPI or other communication protocols