Lead Design Verification Engineer

Design Verification - Prior experience in PCIe,Ethernet,CXL,USB And DDR

Experience: 7 to 12 Years

Notice: 30days to immediate joiner

Location: Bangalore

Qualifications: Bachelor's or Master's degree in Electrical Engineering

Job Summary:

Prior experience in PCIe,Ethernet,CXL And DDR

Good in SV UVM

Strong in SV, UVM, PCIe,Ethernet,CXL,USB

PCIe,Ethernet,CXL,USB networking protocol verification

Preferred Skills:

Experience in leading teams and managing projects.

Knowledge of additional verification methodologies and tools.

Strong communication and interpersonal skills.

Ability to work in a fast paced environment and manage multiple priorities

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