Lead Design Verification Engineer

Lead Design Verification Engineer

Location: Bengaluru, India

Experience: 6–12 Years

About the Role

We're looking for a hands-on Lead Design Verification Engineer to drive functional verification of complex SoC/IP designs. You'll develop scalable verification environments, ensure first-pass silicon success, and collaborate closely with design and architecture teams on next-generation semiconductor products.

What You'll Do

• Develop and execute verification plans for complex SoC/IP blocks.
• Build reusable SystemVerilog/UVM verification environments.
• Verify high-speed interface protocols such as PCIe, CXL, DDR, USB, Ethernet, AXI, or CHI.
• Create assertions, functional coverage, constrained-random tests, and debug complex failures.
• Drive verification closure using coverage-driven methodologies.
• Mentor junior engineers and lead technical execution across projects.

What We're Looking For

• 6–12 years of Design Verification experience.
• Strong expertise in SystemVerilog, UVM, and SVA.
• Proven experience verifying one or more high-speed protocols (PCIe/CXL/DDR/Ethernet/USB/AXI/CHI).
• Strong debugging skills with industry-standard simulators and waveform analysis tools.
• Solid understanding of SoC architecture, verification methodologies, and scripting (Python/Perl/Shell).

Join us to build cutting-edge silicon powering the next generation of computing and connectivity.