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    Job · 10788733

    Altera Corporation logo

    Lead Design Verification Engineer

    Altera Corporation · Bengaluru · onsite · Posted 71d ago

    Undisclosed6–9 yrsfulltimeSourced fromNaukri

    About a minute. You'll make an account on the way through.

    About this role

    Job Details:

    Performs functional logic verification of an FPGA to ensure design will meet specification requirements. Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. May also collaborate with systems and software engineers to support integration testing of the FPGA. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e.g., gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications.

    Qualifications:

    Minimum Qualification:

    Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience.
    Related technical experience should be in/with: Pre Silicon Validation/Verification.
    OVM/UVM, System Verilog, constrained random verification methodologies.

    Preferred Qualification:

    Design Verification with developing, maintaining, and executing complex IPs and/or SOCs.
    The complete verification life cycle (verification architecture, test plan, execution, debug, coverage closure).
    Developing validation test suites and driving continuous improvement into existing validation test suites and methodologies.
    Experience in FPGA architecture or FPGA prototyping

    Job Type: Regular

    Shift: Shift 1 (India)

    Primary Location: Regus, Madhapur

    Additional Locations: Bengaluru, Karnataka, India, Penang 15, Penang, Malaysia

    Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

    Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

    Sourced from naukri

    Skills

    PrototypingFPGA Designphysical designipsbsVerilogUVMSystem VerilogDesign Verificationsilicon validationFunctional VerificationDebugOvmArchitectureIntegration Testing

    Lead Design Verification Engineer · waiting for your command