Lead Design Verification DDR Engineer
Cadence · Bengaluru · onsite · Posted 27d ago
Not disclosed2–4 yrsfulltimeSourced from
About a minute. You'll make an account on the way through.
About this role
- BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.
- 2+ years of Design Verification experience with SV/UVM
- Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
- Design Verification experience verifying complex designs and leading projects from concept to verification closure.
- Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.
- Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.
Sourced from foundit
Skills
DdrUVMSystem VerilogIp VerificationDesign VerificationFunctional VerificationHBMGDDREnvironment DevelopmentTest Plan GenerationMemory IPEnvironment planning
About Cadence
Cadence
San Jose
CR
About
Cadence is a pivotal leader in electronics and system design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world??s most innovative companies, delivering extraordinary electronic products from chips to boards to complete systems for the most dynamic market applications, including hyperscale computing, 5G communications, automotive, mobile, aerospace, consumer, industrial and healthcare. For eight years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For
Industries
AerospaceArtificial Intelligence (AI)BiopharmaElectronic Design Automation (EDA)HardwareMobile