Lead - Design Verification (ASIC/SoC)

Role Overview

Looking for a Lead (Design Verification) with strong experience in SoC verification. The role involves subsystem verification, UVM-based environment development, protocol verification, debugging, and collaboration with design and architecture teams.

Key Responsibilities

• Verify SoC subsystems and integrations
• Develop DV test plans, test benches, and testcases
• Build SystemVerilog/UVM verification environments
• Perform functional verification and coverage closure
• Debug simulation and integration issues
• Work with AXI/AHB/APB-based subsystem verification
• Support gate-level simulation and low-power verification
• Collaborate with architecture, RTL, and ATE teams
• Generate VCD/FSDB files for power analysis and testing

Required Qualifications / Skills

• Bachelor s/Master s degree in Electronics, Electrical, or Computer Engineering
• 10-15 years of SoC/ASIC verification experience
• Strong expertise in ARM architecture and AMBA protocols
• Good experience in SystemVerilog and UVM
• Familiarity with Cadence simulation tools
• Strong debugging and verification skills
• Strong Communication, Interpersonal, Team Management, Problem Solving skills